AMD’s Masterful Utilization of Chiplets to Align with Strategic Execution

**AMD Data Center Premiere Event Unveils New Epyc Processors and Workload Optimization**

*AMD Introduces Bergamo and Genoa-X for Targeted Workloads*

At the recent Data Center & AI Technology Premiere Event in San Francisco, Advanced Micro Devices (AMD) announced the addition of two new products, Bergamo and Genoa-X, to their 4th Gen Epyc portfolio. These processors join the previously released Genoa processor, which is part of AMD’s strategy to deliver the highest performing general-purpose data center CPU and then optimize it for specific workloads. Additionally, AMD gave a glimpse into the fourth product in the portfolio, Siena, which is set to be released later this year. Bergamo is designed for cloud native workloads, Genoa-X is targeted at technical and design applications, and Siena is aimed at communications and intelligent edge applications. Bergamo and Genoa-X are already shipping, while Siena will be available later this year.

**The Power of Epyc Architecture: Genoa and Chiplet Design**

Last November, AMD launched the 4th Gen Epyc architecture with the release of the Genoa processors. These processors feature up to 96 Zen 4 cores, PCIe 5 input/output, CXL support for memory expansion, up to 12 channels of DDR5 memory, and a chiplet architecture. This chiplet design allows for the inclusion of up to 12 core complex die (CCDs) and facilitates the customization of the Genoa processor for specific workloads. By modifying critical component configurations, such as the type of cores used or incorporating AMD’s 3D V-Cache for enhanced L3 cache subsystem, AMD is able to quickly optimize the Genoa design to meet the needs of different workloads.

**Bergamo: Optimal Performance for Cloud Native Workloads**

Cloud native workloads, which focus on applications and development operations (DevOps), require high application and compute density, container and performance scalability, and energy efficiency. To meet these requirements, AMD made targeted modifications to the Genoa processor for the Bergamo design. These modifications were made possible by the chiplet architecture, minimizing technical and manufacturing risks. One significant modification is the use of the Zen4c core, which is 35% smaller than the Zen4 core and utilizes low-power, smaller standard cells. Despite these changes, the Zen4c core maintains complete instruction set compatibility. Additionally, Bergamo achieves higher compute density, enabling 16 cores per CCD and a maximum of 128 cores with eight CCDs per package. AMD estimates that Bergamo offers two to three times better performance in throughput, thread performance, and system efficiency compared to competitors’ solutions. This increased performance translates to fewer servers, lower power consumption, reduced operating expenses, and a lower total cost of ownership for cloud native data centers.

**Genoa-X: Optimized for Technical Computing Workloads**

Technical computing workloads, which include research and design applications that require large memory bandwidth, benefit from the Genoa-X processor. Genoa-X is based on the same Zen4 cores and CCD configuration as Genoa, with the addition of AMD’s 3D V-Cache chiplet technology. This technology enables up to 1.1GB of L3 cache, resulting in increased server performance and optimization. Compared to a leading competitor, Genoa-X may reduce the number of servers by up to 43% and consume 38% less power.

**The Role of Chiplet Architecture in Workload Customization**

AMD’s use of chiplet architecture in their Epyc processors allows for quick and efficient customization for specific workloads. While chiplets are still relatively new in the merchant market, AMD’s successful implementation showcases their effectiveness in addressing business challenges such as strategic execution, time to market, revenue growth, and margin expansion.

In conclusion, AMD’s Data Center Premiere event introduced new additions to their 4th Gen Epyc portfolio, including Bergamo and Genoa-X, designed for targeted workloads. These processors leverage the power of the Epyc architecture and the flexibility of chiplet design to optimize performance and efficiency. By making modifications to critical components, AMD can rapidly customize their processors to meet the needs of diverse workloads. This approach results in improved performance, reduced power consumption, and a lower total cost of ownership for data centers.

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