AMD Introduces Cutting-Edge Design Emulation Chip, the World’s Largest Programmable and Adaptive

**Title: AMD Introduces Versal Premium VP1902 Adaptive SoC for Advanced Chip Design**

**AMD Versal Premium VP1902 Adaptive SoC**

This morning, AMD unveiled its new Versal Premium VP1902 adaptive System on Chip (SoC) products, marking a significant milestone in semiconductor chip design. These new SoCs aim to address the challenges and costs associated with designing the next generation of processors, accelerators, and platform products. To achieve this, AMD leverages Field Programmable Gate Arrays (FPGAs), which serve as both a virtual and physical sandbox for chip engineers to design and emulate their creations before moving on to expensive production processes.

**Why Build The World’s Largest Programmable, Adaptable Chip**

To meet the growing demand for compute power and new functionality, which is being driven by applications like AI, engineers need FPGAs with a high density of programmable logic gates. AMD’s Versal Premium VP1902 adaptive SoC addresses this limitation by offering 2X the programmable logic density compared to the previous generation Virtex UltraScale+ products. In fact, it boasts the title of the world’s largest adaptive SoC, featuring 18.5 million logic cells and 2X the aggregate IO bandwidth. In contrast, AMD’s nearest competitor, Intel, tops out at 10 million logic elements with its Stratix 10 GX.

**Versal Premium VP1902 Adaptive SoC Features And Aggregate Bandwidth**

Built on TSCM’s 7nm process, the Versal Premium VP1902 adaptive SoC from AMD offers exceptional programmable logic density and aggregate IO bandwidth. With its 18.5 million logic cells, this chip provides chip designers with a massive space to implement complex designs. Furthermore, the SoC delivers 2X the aggregate IO bandwidth compared to the previous generation, ensuring enhanced performance and capabilities.

**Versal VP1902 High Level Block Diagram**

AMD achieves its Versal Premium logic density advantage by employing a new quadrant-based architecture that utilizes partitioning. This approach is similar to chiplets, with the addition of a high-speed Network on Chip (NoC) that connects multiple partitions and enables the AMD-Xilinx Versal VP1902 FPGA to function seamlessly. This design allows chip designers to confidently emulate and prototype next-generation products in various areas, including AI, autonomous vehicles, Industry 5.0, and other emerging technologies.

**Debugging Performance And Software Tools Are Key for Customer Time To Market**

In addition to its exceptional density and throughput, the Versal VP1902 features unmatched debug capabilities. With the help of the NoC, debugging speeds are up to 8X faster compared to the previous generation VU19P FPGA portfolio. AMD has also enhanced its Vivado ML design suite of tools to support development on VP1902 FPGAs. These tools come with automated design closure assistance, interactive design tuning, remote multi-user real-time debugging, and improved back-end compilation of designs. All these features empower engineers to refine and improve their chip designs more efficiently and with greater speed.

**AMD’s Synergy With Xilinx Technology**

Since its acquisition of Xilinx, AMD has shown clear synergy between the two companies. Xilinx’s adaptable technology has proven valuable across AMD’s combined product portfolio, from the client and cloud data center to automotive, aerospace, and AI markets. While Versal is a core Xilinx technology exclusively designed to address unique, large-scale design challenges, it is evident that the combined team and technology portfolio continue to evolve and demonstrate strength.

**Future Availability**

AMD’s Versal Premium VP1902 FPGAs will be available for sampling in Q3 ’23, with production set for the first half of 2024. The software design tools will be released in the second half of 2023, providing engineers with a comprehensive solution for their chip design needs.

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